Manufacture of various semiconductor devices such as memory devices, logic devices, and microprocessors has the common goal of miniaturization. As feature sizes decrease, the electrical operation of the transistor becomes more difficult. One contributing factor to this difficulty is known as the “short channel effect” in which the width of the transistor channel becomes excessively small due to miniaturization. This may result in the transistor activating even though a threshold voltage (Vt) has not been applied to the gate.
One type of transistor which has been developed to overcome the short channel effect of a conventional transistor by forming a wider channel in the same horizontal space is referred to as a “recessed access device” or “RAD ” transistor. One type of RAD transistor comprises a transistor gate (word line) which is partially formed within a trench in a semiconductor wafer. The channel region is formed along the entire surface of the trench which, in effect, provides a wider channel without increasing the lateral space required by the transistor.
A conventional method to form an n-channel metal oxide semiconductor (NMOS) RAD transistor is depicted in FIGS. 1-6. FIG. 1 depicts a semiconductor wafer 10 having a region 12 which is doped with n-type dopants, a pad oxide (pad dielectric) 14 which protects the wafer 10 from a patterned mask 16, which is typically photoresist. An anisotropic etch is performed on the FIG. 1 structure to form the trench 20 within the wafer 10 as depicted in FIG. 2. The transistor channel 22 is formed within the wafer along the trench, and results from a conductively doped region within the wafer.
After forming the FIG. 2 structure, the photoresist 16 and the pad oxide 14 are removed and a transistor gate oxide layer 30 is formed over the exposed semiconductor wafer 10. Next, various blanket transistor gate layers are formed as depicted in FIG. 3, such as a doped polysilicon layer 32, a silicide layer 34, and a nitride capping layer 36. A patterned photoresist layer 38 is formed which will be used to define the transistor gate. The FIG. 3 structure is anisotropically etched down to the gate oxide, and the photoresist layer 38 is removed to result in the transistor gate of FIG. 4 which comprises layers 32, 34, and 36. A blanket spacer layer 50, for example silicon nitride, is formed over the structure of FIG. 4 to result in the FIG. 5 structure, and a spacer etch is then performed to form insulative spacers 60 around the transistor gate as depicted in FIG. 6, and to complete the transistor gate. In the structure of FIG. 6, implanted regions 12 represent transistor source/drain regions, although other implanting steps may be performed which are not immediately germane to the present invention.
The structure of FIGS. 1-6 is formed using an ideal process. A not-infrequent problem with semiconductor device formation, particularly with decreasing feature sizes, is misalignment of a photoresist mask. This may result in the process and structure depicted in FIGS. 7-10. FIG. 7 comprises a structure analogous to FIG. 3 wherein the mask 38 of FIG. 3 has been misaligned to result in mask 70 of FIG. 7.
After forming the FIG. 7 structure, capping nitride layer 36, silicide layer 34, and polysilicon layer 32 are etched to result in the defined gate of FIG. 8. This etch, because of the misalignment of the mask 70, removes a portion of the polysilicon layer 32 from the trench along trench portion 80 and exposes the channel region 22 as depicted.
Wafer processing continues according to the method of FIGS. 1-6 to form spacer layer 50 as depicted in FIG. 9, then a spacer etch is performed to result the device of FIG. 10 comprising insulative spacers 60.
The transistor of FIG. 10 will have poor electrical operation and may even be nonfunctional. The application of the threshold voltage across the transistor requires adequate electrical communication between the gate (layers 32 and 34) and each of the channel region 22 and the source/drain regions 12. As depicted in FIG. 6, the gate overlies the entire channel region 22 and also the source/drain region 12 on each side of the channel 22. As depicted in FIG. 10, however, the gate 32, 34 does not overlie either of region 80 of the channel 22 or the source/drain region 12 on the left side of the gate. Further, the nitride spacer 60 has a portion interposed between gate layer 32 and region 80 of the channel 22. This electrical insulator between the gate and the channel, along with the increased distance between gate layer 32 and portion 80 of channel 22, decreases electrical coupling between the channel portion 80 and gate layer 32.
A method for forming a RAD transistor gate and a resulting RAD transistor which has more robust tolerance for mask misalignment over conventional processing would be desirable.